The present invention relates in general to fabrication methods and resulting structures for semiconductor devices. More specifically, the present invention relates to fabrication methods and resulting structures for providing at least two fully depleted silicon on insulator (FDSOI) transistor devices each having its buried dielectric charge and threshold voltage different from the other.
Fully depleted silicon on insulator (FDSOI) technology utilizes a very thin film located between the gate and the buried oxide layer ensuring that the depletion region spans the entire region between the source and the drain. By construction, there is no need to add a dopant to the thin film ultimately resulting in a reduced threshold voltage. In order to produce competitive electronic devices though, semiconductor chips with different regions is desired. For example, an existing challenge in FDSOI technology is that forming transistors with voltage threshold control has proved difficult.
One solution to incorporate voltage threshold control into FDSOI technology includes incorporating back gates with different dopants. In this case, independent back gate control for nFET and pFET requires junction isolation. However, heavy doping in the back gate is required to minimize depletion effects and maintain voltage threshold control. Therefore, with ground rule scaling, junction leakage between heavily doped back gates is expected to increase, limiting the back bias range to minimize the PN junction leakage current. Shallow-trench-isolations have been formed in between neighboring transistors in order to prevent junction leakage, but such techniques add significant complexity and cost to the fabrication of the component.
An improved FDSOI transistor device with voltage threshold control is therefore desired.